Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
u0|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
u0|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
u0|rst_controller 33 29 0 29 2 29 29 29 0 0 0 0 0
u0|irq_mapper 5 29 2 29 32 29 29 29 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_009|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_009 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_008 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_007 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_006 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_005 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_004 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_003 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_002 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_001 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux_001|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux_001|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux_001 221 0 0 0 111 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux|arb|adder 36 18 0 18 18 18 18 18 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux|arb 13 0 4 0 9 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux 984 0 0 0 118 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_009 112 1 2 1 110 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_008 112 1 2 1 110 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_007 112 1 2 1 110 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_006 112 1 2 1 110 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_005 112 1 2 1 110 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_004 112 1 2 1 110 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_003 112 1 2 1 110 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_002 113 4 2 4 219 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_001 112 1 2 1 110 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux 112 1 2 1 110 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_009 112 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_008 112 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_007 112 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_006 112 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_005 112 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_004 112 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_003 112 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_002|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_002|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_002 221 0 0 0 111 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_001 112 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux 112 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_demux_001 113 4 2 4 219 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|cmd_demux 120 81 2 81 982 81 81 81 0 0 0 0 0
u0|mm_interconnect_0|router_011|the_default_decode 0 10 0 10 10 10 10 10 0 0 0 0 0
u0|mm_interconnect_0|router_011 102 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_010|the_default_decode 0 10 0 10 10 10 10 10 0 0 0 0 0
u0|mm_interconnect_0|router_010 102 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_009|the_default_decode 0 10 0 10 10 10 10 10 0 0 0 0 0
u0|mm_interconnect_0|router_009 102 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_008|the_default_decode 0 10 0 10 10 10 10 10 0 0 0 0 0
u0|mm_interconnect_0|router_008 102 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_007|the_default_decode 0 10 0 10 10 10 10 10 0 0 0 0 0
u0|mm_interconnect_0|router_007 102 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_006|the_default_decode 0 10 0 10 10 10 10 10 0 0 0 0 0
u0|mm_interconnect_0|router_006 102 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_005|the_default_decode 0 10 0 10 10 10 10 10 0 0 0 0 0
u0|mm_interconnect_0|router_005 102 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_004|the_default_decode 0 10 0 10 10 10 10 10 0 0 0 0 0
u0|mm_interconnect_0|router_004 102 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_003|the_default_decode 0 10 0 10 10 10 10 10 0 0 0 0 0
u0|mm_interconnect_0|router_003 102 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_002|the_default_decode 0 10 0 10 10 10 10 10 0 0 0 0 0
u0|mm_interconnect_0|router_002 102 0 2 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_001|the_default_decode 0 14 0 14 14 14 14 14 0 0 0 0 0
u0|mm_interconnect_0|router_001 102 0 6 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router|the_default_decode 0 14 0 14 14 14 14 14 0 0 0 0 0
u0|mm_interconnect_0|router 102 0 6 0 110 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|onchip_memory_s2_agent_rsp_fifo 142 39 0 39 101 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|onchip_memory_s2_agent|uncompressor 34 1 0 1 32 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|onchip_memory_s2_agent 287 39 47 39 298 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|push_button_s1_agent_rsp_fifo 142 39 0 39 101 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|push_button_s1_agent|uncompressor 34 1 0 1 32 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|push_button_s1_agent 287 39 47 39 298 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|watchdog_s1_agent_rsp_fifo 142 39 0 39 101 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|watchdog_s1_agent|uncompressor 34 1 0 1 32 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|watchdog_s1_agent 287 39 47 39 298 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|timer_0_s1_agent_rsp_fifo 142 39 0 39 101 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|timer_0_s1_agent|uncompressor 34 1 0 1 32 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|timer_0_s1_agent 287 39 47 39 298 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sliders_s1_agent_rsp_fifo 142 39 0 39 101 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sliders_s1_agent|uncompressor 34 1 0 1 32 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|sliders_s1_agent 287 39 47 39 298 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|leds_s1_agent_rsp_fifo 142 39 0 39 101 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|leds_s1_agent|uncompressor 34 1 0 1 32 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|leds_s1_agent 287 39 47 39 298 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|onchip_memory_s1_agent_rsp_fifo 142 39 0 39 101 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|onchip_memory_s1_agent|uncompressor 34 1 0 1 32 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|onchip_memory_s1_agent 287 39 47 39 298 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|proc_debug_mem_slave_agent_rsp_fifo 142 39 0 39 101 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|proc_debug_mem_slave_agent|uncompressor 34 1 0 1 32 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|proc_debug_mem_slave_agent 287 39 47 39 298 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sysid_control_slave_agent_rsp_fifo 142 39 0 39 101 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sysid_control_slave_agent|uncompressor 34 1 0 1 32 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|sysid_control_slave_agent 287 39 47 39 298 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo 142 39 0 39 101 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_agent|uncompressor 34 1 0 1 32 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_agent 287 39 47 39 298 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|proc_instruction_master_agent 173 39 78 39 134 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|proc_data_master_agent 173 39 78 39 134 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|onchip_memory_s2_translator 101 7 3 7 88 7 7 7 0 0 0 0 0
u0|mm_interconnect_0|push_button_s1_translator 101 6 19 6 70 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|watchdog_s1_translator 85 22 34 22 55 22 22 22 0 0 0 0 0
u0|mm_interconnect_0|timer_0_s1_translator 85 22 34 22 55 22 22 22 0 0 0 0 0
u0|mm_interconnect_0|sliders_s1_translator 101 6 19 6 36 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|leds_s1_translator 101 6 19 6 70 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|onchip_memory_s1_translator 101 7 3 7 88 7 7 7 0 0 0 0 0
u0|mm_interconnect_0|proc_debug_mem_slave_translator 101 5 9 5 82 5 5 5 0 0 0 0 0
u0|mm_interconnect_0|sysid_control_slave_translator 101 6 17 6 35 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_translator 101 5 20 5 70 5 5 5 0 0 0 0 0
u0|mm_interconnect_0|proc_instruction_master_translator 102 51 0 51 94 51 51 51 0 0 0 0 0
u0|mm_interconnect_0|proc_data_master_translator 102 12 0 12 94 12 12 12 0 0 0 0 0
u0|mm_interconnect_0 368 0 0 0 375 0 0 0 0 0 0 0 0
u0|watchdog 23 0 14 0 17 0 0 0 0 0 0 0 0
u0|timer_0 23 0 0 0 17 0 0 0 0 0 0 0 0
u0|sysid 3 13 2 13 32 13 13 13 0 0 0 0 0
u0|sliders 14 0 0 0 32 0 0 0 0 0 0 0 0
u0|push_button 39 0 31 0 33 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_debug_slave_wrapper|the_first_computer_proc_cpu_debug_slave_sysclk 43 0 0 0 48 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_debug_slave_wrapper|the_first_computer_proc_cpu_debug_slave_tck 130 0 1 0 43 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_debug_slave_wrapper 123 0 0 0 50 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_ocimem|first_computer_proc_cpu_ociram_sp_ram|the_altsyncram|auto_generated 47 0 0 0 32 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_ocimem|first_computer_proc_cpu_ociram_sp_ram 47 0 0 0 32 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_ocimem 92 0 6 0 65 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_avalon_reg 48 0 28 0 68 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_im 54 38 51 38 47 38 38 38 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_pib 0 36 0 36 36 36 36 36 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_fifo|the_first_computer_proc_cpu_nios2_oci_fifo_cnt_inc 5 0 0 0 5 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_fifo|the_first_computer_proc_cpu_nios2_oci_fifo_wrptr_inc 4 2 0 2 4 2 2 2 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_fifo|the_first_computer_proc_cpu_nios2_oci_compute_input_tm_cnt 3 0 0 0 2 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_fifo 115 0 65 0 36 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_dtrace|first_computer_proc_cpu_nios2_oci_trc_ctrl_td_mode 9 0 6 0 4 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_dtrace 103 0 92 0 72 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_itrace 24 53 24 53 53 53 53 53 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_dbrk 88 0 0 0 92 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_xbrk 54 5 51 5 6 5 5 5 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_break 51 36 6 36 71 36 36 36 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci|the_first_computer_proc_cpu_nios2_oci_debug 50 1 30 1 7 1 1 1 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_nios2_oci 156 0 0 0 69 0 0 0 0 0 0 0 0
u0|proc|cpu|first_computer_proc_cpu_register_bank_b|the_altsyncram|auto_generated 44 0 0 0 32 0 0 0 0 0 0 0 0
u0|proc|cpu|first_computer_proc_cpu_register_bank_b 44 0 0 0 32 0 0 0 0 0 0 0 0
u0|proc|cpu|first_computer_proc_cpu_register_bank_a|the_altsyncram|auto_generated 44 0 0 0 32 0 0 0 0 0 0 0 0
u0|proc|cpu|first_computer_proc_cpu_register_bank_a 44 0 0 0 32 0 0 0 0 0 0 0 0
u0|proc|cpu|the_first_computer_proc_cpu_test_bench 288 3 254 3 33 3 3 3 0 0 0 0 0
u0|proc|cpu 149 1 29 1 111 1 1 1 0 0 0 0 0
u0|proc 149 0 0 0 110 0 0 0 0 0 0 0 0
u0|onchip_memory|the_altsyncram|auto_generated|mux5 130 0 0 0 32 0 0 0 0 0 0 0 0
u0|onchip_memory|the_altsyncram|auto_generated|mux4 130 0 0 0 32 0 0 0 0 0 0 0 0
u0|onchip_memory|the_altsyncram|auto_generated|decode3 3 0 0 0 4 0 0 0 0 0 0 0 0
u0|onchip_memory|the_altsyncram|auto_generated|decode2 3 0 0 0 4 0 0 0 0 0 0 0 0
u0|onchip_memory|the_altsyncram|auto_generated 108 0 0 0 64 0 0 0 0 0 0 0 0
u0|onchip_memory 112 1 1 1 64 1 1 1 0 0 0 0 0
u0|leds 38 22 22 22 42 22 22 22 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_r|rfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_r 13 0 1 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_w|wfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart_0|the_first_computer_jtag_uart_0_scfifo_w 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart_0 38 10 23 10 34 10 10 10 0 0 0 0 0
u0 13 0 0 0 10 0 0 0 0 0 0 0 0